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+---
+author: Akbar Rahman
+date: \today
+title: MMME2051 // Digital Electronics
+tags: [ digital, serial, parallel, encoders, shaft_encoders ]
+uuid: 7d355a2f-68c7-4352-a164-7d51006ca137
+lecture_slides: [ ./lecture_slides/MMME2051EMD_Lecture4.pdf, ./lecture_slides/MMME2051EMD_Lecture5.pdf ]
+lecture_notes: []
+exercise_sheets: [ ./exercise_sheets/Exercise Sheet 6 - Digital Electonics 1.pdf, ./exercise_sheets/Exercise Sheet 7 - Digital Electonics 2.pdf ]
+---
+
+<details>
+<summary>
+
+# Errata
+
+</summary>
+
+## Lecture Slides 5, p56
+
+1. The graph showing values of $O_1$, $O_2$, and $O_3$ are incorrect:
+
+  - $O_3$ should stay low throughout
+  - $O_2$ should stay low until after the fourth pulse
+  - $O_1$ should be low until the third pulse, high between third and fourth, and then go back to low
+
+2. There is no mention that $O_4$ is the most significant bit and $O_1$ the least.
+
+## Lecture Slides 5, p62-91
+
+1. The title should be *Digital-to-Analog Converter (DAC)*
+
+</details>
+
+# Shaft Encoder
+
+A shaft encoder can provide angular position, angular speed, and direction.
+
+![A simple shaft encoder which can only detect speed by using a light source and a light dependent resistor.](./images/vimscrot-2023-03-02T11:20:42,254588604+00:00.png)
+
+
+![A motor position encoder provides the angle of the shaft, allowing the angular velocity to be calculated.](./images/vimscrot-2023-03-02T11:21:28,818484079+00:00.png)
+
+
+![An incremental shaft encoder has a pulse Z which gives speed and outputs A and B can be used to detect the direction of rotation as the pulses are phase shited by a quarter cycle.](./images/vimscrot-2023-03-02T11:23:18,428027299+00:00.png)
+
+# Memory in Computers
+
+An OR gate can be used to create a *latch* which will stay high until it is reset:
+
+
+![](./images/vimscrot-2023-03-02T11:27:47,797530860+00:00.png)
+
+![](./images/vimscrot-2023-03-02T11:27:56,816525086+00:00.png)
+
+## Set/Reset Latch
+
+![](./images/vimscrot-2023-03-02T11:28:48,754069731+00:00.png)
+
+An equivalent circuit can be built by replacing the NOR gates with NAND gates and taking NOTing the
+inputs before applying them (lecture 5 slides, p27).
+
+## Enabling a Latch
+
+![The outputs of this circuit will remain constant while E is low.](./images/vimscrot-2023-03-02T11:33:17,227770085+00:00.png)
+
+## Delay Gated Latch
+
+![](./images/vimscrot-2023-03-02T11:34:46,470336694+00:00.png)
+
+This latch allows memory to be set/reset without having a reset line.
+
+# Clock
+
+A clock signal is a square waveform.
+The higher the frequency of the signal, the faster processing can happen.
+One step of processing is expected to happen per clock pulse.
+A clock pulse is usually considered to be its rising edge:
+
+![A clock pulse with the rising edge highlighted in blue and the falling edge in red.](./images/vimscrot-2023-03-02T11:52:38,262923088+00:00.png)
+
+## JK Flip-Flop
+
+Flip-flops differ from latches mainly by the fact
+they are edge triggered (triggered by the edge of the clock pulse, rather than by change in input signals).
+
+$$Q_\text{next} = J \bar Q + \bar K Q$$
+
+Clock | J | K | $Q_\text{next}$ | $\bar Q_\text{next}$
+----- | --- | --- | --- | ---
+0 $\rightarrow$ 1 | 0 | 0 | $Q$ | $\bar Q$
+0 $\rightarrow$ 1 | 0 | 1 | 0 | 1
+0 $\rightarrow$ 1 | 1 | 0 | 0 | 0
+0 $\rightarrow$ 1 | 1 | 1 | $\bar Q$ | $Q$
+
+![](./images/vimscrot-2023-03-02T12:00:50,868501744+00:00.png)
+
+## Serial to Parallel Conversion with JK Flip-Flops
+
+There are [errors](#errata) in lecture slides relating to this section.
+
+![](./images/vimscrot-2023-03-02T12:16:57,368571510+00:00.png)
+
+# Digital to Analog Converter (DAC)
+
+![A 4-bit DAC](./images/vimscrot-2023-03-02T12:30:58,854924598+00:00.png)
+
+$V_\text{out}$ can be expressed as the following:
+
+$$V_\text{out} = \sum D_n\frac{1}{2^n}V_\text{max}$$
+
+where $D_n$ is 1 for an high input and 0 for a low input.
+
+The lecture slides go through the circuitry step by step (lecture 5, p62-91).
+
+# Comparator
+
+![](./images/vimscrot-2023-03-02T12:45:54,622443687+00:00.png)
+
+If the positive input is larger than the negative, the output is high.
+
+# Analog Digital Converter (ADC)
+
+![](./images/vimscrot-2023-03-02T12:48:03,763983627+00:00.png)
+
+Explanation in lecture slides (lecture 5, p93-94) and on flash converters (lecture 5, p95).
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