127 lines
4.1 KiB
Markdown
Executable File
127 lines
4.1 KiB
Markdown
Executable File
---
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author: Akbar Rahman
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date: \today
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title: MMME2051 // Digital Electronics
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tags: [ digital, serial, parallel, encoders, shaft_encoders ]
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uuid: 7d355a2f-68c7-4352-a164-7d51006ca137
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lecture_slides: [ ./lecture_slides/MMME2051EMD_Lecture4.pdf, ./lecture_slides/MMME2051EMD_Lecture5.pdf ]
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lecture_notes: []
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exercise_sheets: [ ./exercise_sheets/Exercise Sheet 6 - Digital Electonics 1.pdf, ./exercise_sheets/Exercise Sheet 7 - Digital Electonics 2.pdf ]
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---
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<details>
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<summary>
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# Errata
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</summary>
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## Lecture Slides 5, p56
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1. The graph showing values of $O_1$, $O_2$, and $O_3$ are incorrect:
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- $O_3$ should stay low throughout
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- $O_2$ should stay low until after the fourth pulse
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- $O_1$ should be low until the third pulse, high between third and fourth, and then go back to low
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2. There is no mention that $O_4$ is the most significant bit and $O_1$ the least.
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## Lecture Slides 5, p62-91
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1. The title should be *Digital-to-Analog Converter (DAC)*
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</details>
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# Shaft Encoder
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A shaft encoder can provide angular position, angular speed, and direction.
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# Memory in Computers
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An OR gate can be used to create a *latch* which will stay high until it is reset:
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## Set/Reset Latch
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An equivalent circuit can be built by replacing the NOR gates with NAND gates and taking NOTing the
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inputs before applying them (lecture 5 slides, p27).
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## Enabling a Latch
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## Delay Gated Latch
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This latch allows memory to be set/reset without having a reset line.
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# Clock
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A clock signal is a square waveform.
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The higher the frequency of the signal, the faster processing can happen.
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One step of processing is expected to happen per clock pulse.
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A clock pulse is usually considered to be its rising edge:
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## JK Flip-Flop
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Flip-flops differ from latches mainly by the fact
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they are edge triggered (triggered by the edge of the clock pulse, rather than by change in input signals).
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$$Q_\text{next} = J \bar Q + \bar K Q$$
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Clock | J | K | $Q_\text{next}$ | $\bar Q_\text{next}$
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----- | --- | --- | --- | ---
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0 $\rightarrow$ 1 | 0 | 0 | $Q$ | $\bar Q$
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0 $\rightarrow$ 1 | 0 | 1 | 0 | 1
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0 $\rightarrow$ 1 | 1 | 0 | 0 | 0
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0 $\rightarrow$ 1 | 1 | 1 | $\bar Q$ | $Q$
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## Serial to Parallel Conversion with JK Flip-Flops
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There are [errors](#errata) in lecture slides relating to this section.
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# Digital to Analog Converter (DAC)
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$V_\text{out}$ can be expressed as the following:
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$$V_\text{out} = \sum D_n\frac{1}{2^n}V_\text{max}$$
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where $D_n$ is 1 for an high input and 0 for a low input.
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The lecture slides go through the circuitry step by step (lecture 5, p62-91).
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# Comparator
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If the positive input is larger than the negative, the output is high.
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# Analog Digital Converter (ADC)
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Explanation in lecture slides (lecture 5, p93-94) and on flash converters (lecture 5, p95).
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